EXPLORING THE FEASIBILITY OF PARALLEL I2C SENSOR INTERFACING ON AN EDUCATIONAL FPGA BOARD: RESOURCE UTILIZATION ANALYSIS AND DESIGN CONSIDERATIONS

Claudiu-Alexandru OPREA; Botond Sándor KIREI; Romulus Valeriu Flaviu TURCU

doi:10.24193/subbphys.2023.06

Authors

Claudiu-Alexandru OPREA National Institute for Research and Development of Isotopic and Molecular Technologies, Centre of Advanced Research and Technologies for Alternative Energies (CETATEA); Faculty of Electronics, Telecommunications and Information Technology, Technical University, Cluj-Napoca, Romania. https://orcid.org/0000-0003-3805-5827
Botond Sándor KIREI Faculty of Electronics, Telecommunications and Information Technology, Technical University, Cluj-Napoca, Romania. https://orcid.org/0000-0003-4605-5667
Romulus Valeriu Flaviu TURCU National Institute for Research and Development of Isotopic and Molecular Technologies, Center of Advanced Research and Technologies for Alternative Energies (CETATEA), Cluj-Napoca, Romania. *Corresponding author: flaviu.turcu@ubbcluj.ro https://orcid.org/0000-0002-0857-9868

DOI:

https://doi.org/10.24193/subbphys.2023.06

Keywords:

FPGA, sensor, I2C, fast processing, resource usage

Abstract

The goal of this work is to showcase the capabilities of Field Programmable Gate Arrays (FPGAs) as powerful reconfigurable computing devices for educational and research purposes. The work will demonstrate the high processing power of an FPGA by controlling multiple I²C buses to and from peripheral sensors. The article will provide a guide on implementing a state machine in VHDL hardware description language and will present the response of the sensors and the working capacity of Basys 3 FPGA. The I²C signals will be visualized using a Logic Analyzer and explained. The conclusion of the article will highlight the capabilities of FPGAs and explore the potential for their use in other complex tasks.

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